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      "content": "Thanks, frankly I don't think I can commit to this, the next few weeks are packed. That said, I think @Stephan Bökelmann 's `cobedit` would be perfectly suited for this usecase. You should give it a spin.",
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      "content": "1x1 looking good!",
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      "content": "PR raised: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/18\nFeedback welcome!",
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      "content": "I'm about to leave for the airport. \nI'll give it a look real soon. \n\nThank you!!",
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      "content": "Thank you @RebelMike pull request merged\n\nCurrently sitting in airport, so it's difficult to concentrate, but I think they look real good. \n\nFor those at home\n[1x1](https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2Frun-2%2F1x1-cob)\n[p5x1](https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2Frun-2%2F0p5x1-cob)\n[1xp5](https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2Frun-2%2F1x0p5-cob)",
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      "content": "@Tim 'mithro' Ansell if the person who made kicanvas can make it so a render of the die shows up as preview that would be really cool!!",
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      "content": "FWIW I think you could put all the via to have annular rings only at \"Start / End / Connected\"  layers to reduce the cuts in the inners layers.",
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      "content": "I don't think jlc allows blind vias in their regular 4layer cheap version we're using",
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      "content": "That's not blind vias. They still go through and have annular ring on top and bottom .",
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      "content": "ok, @stuart the panel is [ready](https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/run-2/1x1-cob/panelization) but...\n\n@Leo Moser (mole99) @tnt @Tim 'mithro' Ansell @RebelMike \nI think we need to talk about \n- pin1\n- what that means\n- how we want to mark it\n\nI need to get on another flight and don't really have the bandwidth at the moment to come up with a solution.",
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      "content": "looks like 5x2 in that image, did you change to 6x2?",
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      "content": "before I check the gerber files \uD83D\uDE42",
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      "content": "-# also note @RebelMike I changed the vias per @tnt request. Thanks tnt for the suggestion.",
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      "content": "it was always 5x I started with the main one and just chopped off the bottom",
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      "content": "ok, can you please update to 6x2 when you have time? Maybe once we've worked out what we're doing re: the pin 1 marking?",
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      "content": "I don't understand where this request is coming from?",
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      "content": "the bond house said multiples of 4 is most efficient. so 6x2 gives us 3 sets of 4",
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      "content": "per the discussion here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues/11",
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      "content": "I don't actually see anything there about the reason for updating to 6x2, but yeah the bonding house said multiples of 4 is best",
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      "content": "so they have larger chucks than the last place?",
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      "content": "yes",
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      "content": "the factory made this drawing when giving feedback",
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      "content": "ok, gotta go to bathroom and get on plane",
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      "content": "Started a thread.",
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      "content": "Posting to main here, new  panel is 6x2 and we have added a pin1 fiducial. \nConversations still ongoing",
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      "content": "@stuart - Was there something from JLC about panel size or something being the cause of poor connector mounting or something?",
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      "content": "I don't think so",
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      "content": "Turns out you were right about this - after checking for quotation on JLC, the panels are now too small.\n\n@Andrew Wingate apologies but can you please double them up - so we have (6x2)x2 - so two bonding panels per PCBA panel? Like this. This should avoid any additional cost. My bad for not realising this earlier \uD83D\uDE42",
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      "content": "Ok, I've panelized the half slots and have merged @RebelMike pull requests. Thank you again\nI'll look at the p5xp5 tomorrow",
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      "content": "@Andrew Wingate Not sure how we missed this, but there shouldn’t be soldermask between the die and the pins on the quarter slot",
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      "content": "Oof good catch. I'll fix right now, will be a bit before i have internet again",
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      "content": "Thanks!",
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      "content": "Fixed p5xp5 and pushed. Good catch and thanks\n@stuart I went back and double checked them all as a second pass. \nSeemed the v-cut checkbox was turned off on the  p5x1, might be good to regrab them all",
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      "content": "regrabbing now then will place orders",
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      "content": "@Andrew Wingate I just noticed that the 0p5x0p5, 0p5x1 and 1x0p5 BOMs don't have a defined capacitor value.\n\nShould they be 1uFs, the same as for the 1x1s?\n\nAlso for all BOMs is it worth adding the LCSC part number, C19089236?",
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      "content": "Sorry missed that. Yes, 1uF would be great for them all",
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      "content": "I ***think*** the complaint from JLC PCB was about the PCBs being quite thin and warping slightly during the PCBA process causing bad connector adhesion? \n\nDo you know if there are any reasons we use such thin PCB?",
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      "content": "I'm pretty sure that for things like this the actual capacitance doesn't matter hugely, but the capacitor response/type does? https://jlcpcb.com/blog/decoupling-capacitors-guide",
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      "content": "reason for the thin PCB afaik is because you asked for it \uD83D\uDE09\n\nI would be happy to go for thicker in the future if there's no reason not to?",
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      "content": "@stuart re: jlc issue. \nCurrently moving about I'll take a closer look when i get settled somewhere",
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      "content": "Also @stuart can you let me know which board that is. I'll likely just change things to adhere to their specs and give you a new file",
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      "content": "It's the 1x1, all the rest seem to be ok",
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      "content": "@stuart [panels](https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/run-2/1x1-cob/panelization) are ready and new files exported.",
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      "content": "The reason for the thinner PCBs was an attempt to reduce wire lengths, and was also suggested by @tnt if memory serves. \nI think it would be alright to go to 1.0mm or even 1.2mm if we're having problems. 1.6mm would be too chunky for the size of these boards.",
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      "content": "Also the length from the die to the pcb is probably the most determining factor [for decoupling performance]. And having them on the PCB itself gets it as close as possible",
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      "content": "For decoupling 100n is a very outdated value. 1u is definitely a good pick here. But yeah, the trace length and width ( in general the inductance ) will be a big factor for the performance. GF180 drivers have pretty fast edges and I was seeing a lot of ringing and ground bounces on the TT dies from run 1.",
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      "content": "We have been using 1uF",
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      "content": "Thanks, re-order placed",
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